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IEEE Blended Learning Program > Courses > VLSI > Static Timing Analysis for VLSI Engineers
VLSI
Static Timing Analysis for VLSI Engineers
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Self Paced

Last Update:

February 21, 2023

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Static Timing Analysis for VLSI engineers

About Course

In the VLSI industry, knowledge of core STA concepts is essential to deliver perfectly timed digital designs. To that end, this course will train you to achieve timing closure in pre- and post-layout stages, and effectively collaborate with implementation and physical design teams.

Mastering these STA concepts will empower you to close design timings with greater accuracy, and secure your future in VLSI and ASIC.

What is the objective of this course?

To equip VLSI engineers with STA techniques for pre- and post-layout timing closure of digital designs

What Will You Learn?

  • To produce perfectly timed digital designs and build a career in VLSI design
  • Board system design and ASIC design

Course Content

Introduction to Timing Analysis

Basic Terminologies used in STA

Basics of Timing Analysis – Part I

Basics of Timing Analysis – Part II

Clocks and their Characteristics

Timing Exceptions and Back Annotation

PVT Variations and their Effect on Timing

Understanding Timing Reports – Part 1

Understanding Timing Reports – Part 2

Introduction to Effect of Clock Skew on Timing and Fixing Timing Violations

Advanced Concepts in STA – Part I

Advanced Concepts in STA – Part II

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₹10,000.00 ₹17,700.00
  • Expert
  • Instructor
    Self Paced
  • Language
    English

Payment :

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Material Includes

  • E-Learning Modules
  • E-Labs
  • Quizzes & Assessment after each module
  • Final Assessment

Requirements

  • Knowledge of IC Design or completion of ASIC Design Flow course
  • Completion of following BLP courses:
  • Introduction to Logic Design
  • Introduction to Logic Design
  • Working knowledge of Linux and/or Unix
  • Familiarity with Verilog Gate-level netlist syntax

Audience

  • New employees and practicing engineers working in VLSI design (backend), board system design, and ASIC design
  • Managers new to supervising VLSI design teams
  • Employees seeking to move to a lateral entry position as a Timing Engineer
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