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Course Details

Advanced Verification using System Verilog – Corporates Only

Self Paced

Last Update:

February 21, 2023

VLSI - Advanced Verification using System Verilog

About Course

If you’re looking to avoid high verification costs, this corporate-only BLP course is for you. It will explore easier hardware verification and debugging processes through SystemVerilog, as well as its test bench architecture.

Learn how SystemVerilog also allows reuse of design and verification IPs, and enables advanced verification methodologies.

What is the objective of this course?

To cover core concepts of SystemVerilog-based verification and test bench architecture

What Will You Learn?

  • To reduce design cycle times and hardware debugging costs for your business
  • To empower yourself to deliver optimized, faster technologies
  • To qualify yourself for a career in RTL Verification Engineering
  • Review specifications of a digital design and develop a complete and comprehensive verification plan for the same
  • Achieve 100% functional and code coverage by applying SystemVerilog-specific constructs and Object-oriented Programming concepts to test cases and/or regressions
  • Model and develop SystemVerilog test bench architecture for a given RTL design
  • Perform functional simulations to validate and debug designs using an industry-standard RTL simulator
  • Apply for entry-level jobs as RTL Verification Engineer

Course Content

Introduction to SystemVerilog

Commonly Used terminologies in SystemVerilog

Data Types

Object Oriented Programming (OOP) Concepts

The SV Stratified Event Queue/Scheduler

Verification Planning and SV Testbench Architecture

Tasks and Functions

Verification Specific SV constructs

Modeling Transactors

Functional Coverage

Verification Plan and SystemVerilog Testbench Architecture

Modeling Testbench Blocks*


Universal Verification Methodology (UVM)


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10,000.00 35,400.00
  • Instructor
    Self Paced
  • Language

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Material Includes

  • E-Learning Modules
  • E-Labs
  • Quizzes & Assessment after each module
  • Final Assessment


  • Knowledge of RTL Design using Verilog
  • Familiarity with HDL-based verification
  • Working knowledge of Linux and/or Unix
  • Successful completion of the below IEEE BLP courses:
  • Logic Design for VLSI Engineers
  • RTL Design using Verilog
  • RTL Verification using Verilog


  • New employees going through on-board training in design and verification
  • Practicing engineers in the verification domain aspiring to acquire competency in HVL-based verification
  • Employees interested in lateral entry positions as Verification Engineers