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Course Details

IEEE Blended Learning Program > Courses > VLSI > RTL Design using Verilog HDL
VLSI
RTL Design using Verilog HDL
Teacher

Self Paced

Last Update:

February 21, 2023

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RTI design using Verilog HTL - VLS

About Course

To design or review microarchitecture, one needs to have a clear grasp of Register Transfer-level (RTL) coding through the Verilog Hardware Description Language (HDL). And now, you can learn both and boost your skills in Logic Design with this Blended Learning course.

By the end, you will have all the skills necessary to build a fruitful career in the booming RTL design industry.

What is the objective of this course?

This course will introduce you to RTL design through Verilog HDL, while reinforcing your Logic Design skills. You will also understand the full scope of work that comes with being an RTL Design Engineer, and learn the essential terminologies to network with other engineers in the industry.

 

By the end of this course, you will be able to efficiently review the specifications of a digital design, and fully develop and code its microarchitecture.

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What Will You Learn?

  • Learning digital design through Verilog HDL will establish your foundation for a career in RTL design and engineering.
  • Verilog is the industry standard for Hardware Design Languages that are used to design and review microarchitecture. Learning it will not only strengthen your Logic Design skills, but will also help you break into RTL Design Engineering with minimal knowledge gaps.

Course Content

Introduction to digital design using HDLs

Definitions and commonly used terminologies

Overview of frequently used Verilog constructs

Hardware inference of Verilog code

General coding guidelines in Verilog

Modeling FSMs and memories in Verilog

Evolution of Verilog standards

Deliverables of an RTL design engineer

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₹6,000.00 ₹17,700.00
  • Expert
  • Instructor
    Self Paced
  • Language
    English

Payment :

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Material Includes

  • E-Learning Modules
  • E-Labs
  • Quizzes & Assessment after each module
  • Final Assessment

Requirements

  • Working knowledge of Linux/Unix commands
  • Completion of IEEE BLP course on Logic Design for VLSI Engineers
  • Knowledge of Logic Design principles
  • Fundamentals of digital design or completion of Logic Design for VLSI Engineers course

Audience

  • Students enrolled in a UG/PG engineering program
  • New hires working in the RTL design group
  • Experienced engineers with no background in RTL design, who are interested in lateral moves (Ex.: A board design engineer looking to move into SoC RTL design)
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