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IEEE Blended Learning Program > Courses > VLSI > RTL Verification using Verilog
VLSI
RTL Verification using Verilog
Teacher

Self Paced

Last Update:

February 21, 2023

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RTL Verification using Verilog

About Course

Verification is an important process in the design of digital technologies, involving early detection of bugs to avoid huge debugging and isolation costs. The key to this is the latest RTL verification technologies such as Verilog, which you can master through this IEEE BLP course.

What is the objective of this course?

This course is designed to help you understand core concepts of RTL verification, and become proficient in the latest verification technologies.

Thanks to the rising demand for high-power, low-cost electronic devices, Integrated Circuits (ICs) and their design have continued to evolve year by year. This calls for faster and more effective RTL verification to remove bugs and deliver problem-free devices. And to prepare you for this scenario, this course will teach you key verification concepts, and help you master Verilog.

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What Will You Learn?

  • Create a verification plan for simple designs
  • Build verification environment
  • Write test cases and test benches
  • Debug an RTL design
  • Perform RTL simulation using industry standard tools
  • Measure coverage metrics against a given design specification
  • Achieve code coverage goals
  • Mastering RTL verification is important for one simple reason -- to deliver products that function properly and make money. An unverified product or chip could be full of design bugs, which, when left undetected, lead to defective designs. This then results in extra expenses and time spent on debugging and isolation.
  • By taking this IEEE BLP course, you can equip yourself with industry-standard technology and skills needed to debug integrated circuits on time and deliver optimal devices.

Course Content

Introduction to RTL verification

Evolution of verification process

Overview of basic concepts and terminology

Introduction to a test bench

Introduction to verification planning

Development of a verification plan for an Arithmetic Logic Unit (ALU)

Test bench development and simulation

Running the test bench on an RTL simulator (demo)

Overview of advanced terminologies and concepts

Advances in RTL verification

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₹6,000.00 ₹17,700.00
  • Expert
  • Instructor
    Self Paced
  • Language
    English

Payment :

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Material Includes

  • E-Learning Modules
  • E-Labs
  • Quizzes & Assessment after each module
  • Final Assessment

Requirements

  • Working knowledge of Linux/Unix
  • Prior knowledge of Logic Design OR Completion of IEEE Blended Learning course on Logic Design for VLSI Engineers
  • Prior knowledge of RTL Design using Verilog HDL OR Completion of IEEE Blended Learning course on RTL Design using Verilog HDL

Audience

  • College students pursuing UG/PG Engineering, Polytechnic, and Basic Science programs
  • College students pursuing UG/PG Engineering, Polytechnic, and Basic Science programs
  • Academic faculty that teach RTL verification courses
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